Network Processor – Call for Papers – HPCA-12

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.
Topics of interest include, but are not limited to: ·
Processor architectures ·
Cache and memory systems ·
Parallel computer architectures ·
Impact of technology on architecture ·
Power-efficient architectures and techniques ·
High-availability architectures ·
High-performance I/O systems ·
Embedded and reconfigurable architectures ·
Interconnect and network interface architectures ·
Network processor architectures ·
Innovative hardware/software trade-offs ·
Impact of compilers on architecture ·
Performance evaluation of real machines
Authors should submit an abstract before Monday, July 11, 2005, 9pm PST. They should submit the full version of the paper before Monday, July 18, 2005, 9pm PST. No extensions will be granted. The full version should be a PDF file that does not exceed 6,000 words according to the instructions in http://www.hpcaconf.org/hpca12
Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Papers should be submitted for blind review. Please indicate whether the paper is a student paper for best student paper nominations.Papers will be evaluated based on their novelty, fundamental insights, and potential for long-term contribution.
New-idea papers are encouraged.
Submission issues should be directed to the program chair at das@cse.psu.edu. Workshop and tutorial submissions should be directed to the workshop and tutorial chair.
Important dates·
Abstract submission deadline :
July 11, 2005, 9pm PST (firm deadline) ·
Paper submission deadline:
July 18, 2005, 9pm PST (firm deadline) ·
Workshop and tutorial proposals due:
August 12, 2005 ·
Author notification: October 7, 2005
Sponsored by the IEEE Computer Society TC on Computer Architecture

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