Archive for Network Processor

Intel Network Processor Division may be sold off

TIPPINST – Rumors are mounting that the IXP division of Intel responsible for their NP products may be sold off. The Register cites an article in the news paper the San Jose Mercury who have claimed to have seen documents relating to the sale. The Intel’s IXP network processor and its Xscale business – which made mobile chips for phones and other mobile devices are being sold off as a single business according to the paper. The IXP wing of the business generated income of $150 million in 2005. The title of the article in the Mercury “How Intel Wasted Billions” sums up the motivation for this review of their communication business.
This sale could have serious ramification for academic research into multi-processor SOC’s and NP related work. Intel through their Academic Programme have fostered and promoted a very strong research programme with Institutions world wide. I suspect that more will be learned when I attend the ANCS conference in San Jose in Dec 06. Academics and research students (that includes yours truly) will have to wait and see what developments will arise.

DSD2006 – Author Final Paper and Submission Instructions

TIPPINST – If you have been notified about having a paper accepted for the DSD 2006 conference but as of yet have not received the author kit, I would recommend that you visit the DSD 2006 Author page on computer.org. All necessary instructions and latex templates are available on this page.

Dissertation advice – Bedtime Reading For People Who Do Not Have Time To Sleep

TIPPINST – The Department of Computer Science at Pudue University have some pratcial advice for those of you who are contemplating writing a technical report or thesis. Topics covered include
– Definitions And Terminology
– Terms And Phrases To Avoid
– Voice
– Tense
– Defining Negation Early
– Grammar and Logic
– Concept vs Instance
– Terminology For Concepts And Abstractions
– Drawing Only Warranted Conclusions
I would recommend that third level students would read this as many of the topics cover grammatical problems that we see every year.
Dissertation Advice

Megahertz Myth

For a simple but detailed instruction as to how a CPU operates and what its dependencies are check out the following Megahertz Myth presentation on youtube.com
Steve Jobs and John Rubinstein at a presentation for Macworld in 2004 about why CPU speed is not the only consideration when determining how fast a computer really is. A 867 Mhz PowerMac goes head to head with a Pentium 4 – 1.86 Ghz machine.

ANCS 06 – Call for papers – Dec 3rd – 5th San Jose

CALL FOR PAPERS
2nd Symposium on Architectures for
Networking and Communications Systems (ANCS 2006)
http://www.ancsconf.org
December 3-5, 2006
San Jose, California, USA
Sponsored by (pending official renewal):
ACM Special Interest Group on Computer Architecture (SIGARCH)
ACM Special Interest Group on Communications (SIGCOMM)
IEEE Computer Society Tech. Committee on Computer Architecture
IEEE Communications Society Tech. Committee on Computer Communications
ANCS is a research conference that focuses on the design of the
hardware and software components used to create modern communication
networks. The combination of increasing network line speeds and
expanding functional requirements pose continuing and growing
challenges for system designers. New technology elements, including
network processors, content addressable memories, configurable logic
and special-purpose components offer new opportunities for meeting
these challenges, but also raise a variety of new issues. ANCS focuses
on architectures for networking and communication in the broad sense,
including novel architectures, architectural support for advanced
communication, algorithms and protocols for advanced architectures,
software and applications for next-generation networking
architectures, and methodology and benchmarking for evaluating
advanced communication architectures.
Areas of interest include, but are not limited to:
* Network/communications processors
* Intelligent co-processors
* Router architectures
* Switch fabrics/interconnection networks
* Link scheduling, processor/thread scheduling, switch scheduling
* Network adaptors
* Application-specific networks (e.g. SAN)
* Programmable /extensible networks
* Secure communication
* Traffic management
* Packet classification
* Content inspection and filtering
* Energy-efficient designs
We particularly encourage submissions containing highly original
ideas. Submissions will be judged on originality, significance,
interest, clarity, and correctness.
The PAPER DEADLINE for submissions is July 17, 2006 at 11:59PM PST
(US). NO FURTHER EXTENSIONS WILL BE GRANTED. ANCS will use
double-blind reviewing, so submitted papers should not include the
authors’ names.
Paper registration and submission must be done electronically through
EDAS (edas.info). Registration, including the abstract, must be
completed no later than July 10, 2006 at 11:59PM PDT (US). All papers
must be submitted in PDF format for letter-size paper. Submissions
must be viewable by Adobe Acrobat Reader (version 5.0 or higher) and
should not exceed 7,000 words or 10 pages of conference paper format
using 10 pt fonts. Submissions exceeding the required limit will not
be reviewed by the program committee. Camera-ready versions of the
accepted papers will be required to use the ACM SIG format
(www.acm.org/sigs/pubs/proceed/template.html).
Like other conferences, ANCS requires that papers not be submitted
simultaneously to any other conferences or publications, that
submissions not be previously published, and that accepted papers not
be subsequently published elsewhere.
All submissions will be acknowledged by September 22, 2006. If your
submission is not acknowledged by this date, please contact the
program chairs promptly at ancsTPC@arl.wustl.edu.
IMPORTANT DATES
Paper registration and abstract: July 10, 2006
Submission deadline: July 17, 2006
Author notification: September 22, 2006
Final camera-ready copy: October 15, 2006
CONFERENCE ORGANIZATION
General Chair
*************
Laxmi Bhuyan, UC-Riverside
Program Co-Chairs
*****************
Michel Dubois, University of Southern California
Will Eatherton, Cisco Systems
Program Committee
*****************
Gregory Byrd, North Carolina State University
Patrick Crowley, Washington University in St. Louis
Chita Das, Pennsylvania State University
Jose Duato, Technical University of Valencia
Hans Eberle, Sun Microsystems
Manolis Katevenis, University of Crete
T. V. Lakshman, Lucent Technologies
Dan Lenoski, Nuova Impresa
Robert Olsen, Cisco Systems
Vijay Pai, Purdue University
Dhabaleswar Panda, Ohio State University
Scott Rixner, Rice University
Umar Saif, MIT
Tim Sherwood, UC Santa Barbara
Dimitrious Stiliadis, Bell Labs
Chuck Thacker, Microsoft
Jon Turner, Washington University in St. Louis
George Varghese, UCSD
Srnivasan Venkatachary, Netlogic
Harrick Vin, UT Austin
Bapi Vinnakota, Intel
Tilman Wolf, UM Amherst
Steering Committee
******************
Alan Berenbaum, Consultant
Patrick Crowley, Washington Univ. at St. Louis
Mark Franklin, Washington Univ. at St. Louis
Haldun Hadimioglu, Polytechnic Univ.
Nick McKeown, Stanford Univ.
Peter Z. Onufryk, IDT K. K. Ramakrishnan, AT&T Labs

Symposium on Architectures for Networking and Communications Systems 2006

Tippinst – ANCS which used to be the Network Processor workshop in HPCA has jsut announced its dates for its second conference. It will take place in San Jose from December 3rd to 5th 2006. The call for papers will be announced soon.

Network processors being utilised in VOIP

TIPPINST – Its a sign of the times that Network Processors are playing a central role in the delivery of VOIP. This market segment has huge potential for NP manufacturers. One of the first manufacturers of the block is AMCC. AMCC’s nP7250 network processors and nPX5710 and nPX5720/25 traffic managers are being utilized in Acme Packet’s Net-Net(R) SR (session router) and Net-Net(R) SD (session director) devices.
AMCC’s nP7250 offers Layer 2, 3, 4, and above packet and cell processing at wire speed for multi-service cell/packet switching and routing systems in both clear channel (OC-48c) and multi-channel (OC-48, 4xOC-12, 2xGE, 16xOC-3) modes. The nP7250 combines gluelessly with AMCC’s traffic manager, switch fabric, framer, MAC, and search coprocessor products.
The two-chip nPX5700 platform is comprised of the 10-Gbps nPX5710 Traffic Manager and nPX5720/25 Data Manager. The nPX5710 is responsible for admission control, scheduling and queuing functions while the nPX5720/25 manages cell payload memory. Each nPX5710 provides one half of a 10-Gbps full-duplex, fully programmable packet or cell processing solution.
Press Release

Call for Papers – DSD 06 – 9th international conference

TIPPINST – A call for papers has been issued for dsd 06. Having presented at this conference I can highly recommend it.
@@@@@@@@@@@@@@@@@@@@@ DSD 2006 CALL FOR PAPERS@@@@@@@@@@
DSD’2006
9th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN
Architectures, Methods and Tools
Cavtat near Dubrovnik, Croatia
August 30th – September 1st, 2006
SECOND Call for Papers
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Important Dates:
Submission of papers: March 1st, 2006
Notification of acceptance: May 3rd, 2006
Deadline for final version: June 9th, 2006
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Euromicro Conference on Digital System Design (DSD) addresses all aspects of
(embedded) digital and mixed hardware/software system engineering.
It is a discussion forum for researchers and engineers working on state-of-the
art investigations, development, and applications.
It focuses on advanced system, design, and design automation concepts,
paradigms, methods and tools, as well as, modern implementation technologies
that enable effective and efficient development of high-quality (embedded)
systems for important and demanding applications in fields such as (wireless)
communication and networking; measurement and instrumentation; health-care and
medicine; military, space, avionic and automotive systems; security; multi-media
and ambient intelligence.
The main areas of interest are the following:
T1: Systems-on-a-chip/in-a-package: generic system platforms and platform-based
design; network on chip; multi-processors; system on re-configurable chip;
system FPGAs and structured ASICs; rapid prototyping; asynchronous systems;
power, energy, timing, predictability and other quality issues; intellectual
property, virtual components and design reuse.
T2: Programmable/re-configurable architectures: processor, communication, memory
and software architectures with focus on application specific and/or embedded
computing, co-processors; processing arrays; programmable fabrics; embedded
software; arithmetic, logic and special-operator units.
T3: System, hardware and embedded software specification, modeling and
validation: design languages; functional, structural and parametric
specification and modeling; simulation, emulation, prototyping, and testing at
the system, register-transfer, logic and physical levels; co-simulation and co
verification.
T4: System, hardware and embedded software synthesis: system, hardware/software
and embedded software synthesis; behavioral, register-transfer, logic and
physical circuit synthesis; multi-objective optimization observing power,
performance, communication, interconnections, layout, technology, reliability,
robustness, security, testability and other issues; (dynamic) management of
computational resources, power, energy etc.; design environments for embedded
systems and re-configurable computing.
T5: Emerging technologies, system paradigms and design methodologies: optical,
bio, nano and quantum technologies and computing; self-organizing and self
adapting (wireless) systems; wireless sensor networks; ambient intelligence and
augmented reality; ubiquitous, wearable and implanted systems; deep sub-micron
design issues.
T6: Applications of (embedded) digital systems with emphasis on demanding and
new applications in fields such as: (wireless) communication and networking;
measurement and instrumentation; health-care and medicine; military, space,
avionic and automotive systems; security; multi-media, instrumentation and
ambient intelligence; health-care and medicine; military, space, avionic and
automotive systems; security; multi-media and ambient intelligence.
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Special Topics and Sessions:
ST1 (keynote): Design Methodology for Integrated Digital RF, Texsas Instruments
Dr. Roman Staszewski
Design Manager, DRP Design, WTBU
Texas Instruments
SUMMARY:
Both digital and RF/analog designers can claim they have proven and sufficient
design methodologies. The luxury of isolation let them perfect their own world
without any concern for the other. But, the world demands efficiency, the latest
technology for pennies. While tight integration of RF and digital in SOC is the
cost effective answer, it opens a design methodology Pandora Box. What
previously could be ignored, has to be considered. What was proven and
sufficient, may not work anymore. The resulting paradigm change affects all
aspects of the design process from system architecture to circuit design to
validation to test.
SS1: Resource-Aware Sensor Network Systems
SCOPE: The special session on “Resource-Aware Sensor Network Systems” addresses
concepts, implementations and applications of sensor network systems, as well
as, new architectural models and hardware solutions in the sensor network
domain. Papers on any of the following and re-lated topics will be considered
for the special session:
• Sensor network concepts and architectures
• Sensing, processing and communicating on a chip
• Low-power and low-energy computation and communication
• Communication-computation trade-offs
• Resource-aware SW/HW Co-design
• Position determination and synchronization in sensor networks
• Fault-tolerance, dependability and robustness
• Prototypes and applications
SESSION ORGANIZER:
M. Handy, University of Rostock (DE)- matthias.handy@uni-rostock.de
SPECIAL SESSION SS1 WEB PAGE:
http://www-md.e-technik.uni-rostock.de/ma/hm13/dsd06
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Special Session SS2: Low-Power and High-Performance Networks-on-Chip
SCOPE
Although this special session addresses all aspects related to concepts,
implementations and applications of networks-on-chip and related EDA tools, its
focus is on low-power and high-performance aspects. Papers on any of the
following and related topics will be considered for the special session:
• Network-on-Chip concepts and architectures
• Application-specific communication on a chip and network topology
• Routing schemes, switch concepts, layouts, and signal transmission
• Low-power, low-energy and high-performance computation and communication
• Communication/computation and energy/performance trade-offs
• Static power minimization and dynamic power management
• Data coding, error detection, fault-tolerance and robustness
• Prototypes and applications
Session Organizer:
C. Cornelius, University of Rostock (DE) – claas.cornelius@uni-rostock.de
Special Session web page:
http://www-md.e-technik.uni-rostock.de/ma/cc14/dsd06/
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Panel Sessions and Embedded Tutorials:
Proposals for panel sessions and embedded tutorials are especially welcome.
Please contact Program Chair (venki@dsdconf.org).
Submission of papers:
Regular Papers: Submissions can be made that describe innovative work in the
scope of the Conference, and especially, in any of the above main areas of
interest (please indicate the topic area). If you are submitting to a track
please indicate the track area on the paper as: SS1 or SS2. Prospective authors
are encouraged to submit their manuscripts for review electronically trough the
following web page (http://www.dsdconf.org/) or by sending the paper to the
Program Chair via email venki@dsdconf.org (only in the case of the web
access problem) before the deadline for submission. Each manuscript should
include the complete paper text, all illustrations, and references. The
manuscript should conform to the required format single-spaced, double column,
A4/US letter page size, 10-point size Times Roman font, up to 8 pages. In order
to conduct a blind review, no indication of the authors’ names should appear in
the submitted manuscript.
Case Study and Application Papers: Submissions can be made which report on
state-of-the-art digital systems, design methods and/or tools, and (embedded)
applications. Papers discussing lessons learned from practical experience,
demanding or new applications, and experimental research are particularly
encouraged. Manuscripts may be submitted in the same way as regular papers.
The Program Committee will decide if papers will be accepted for a long
presentation (30 minutes), short presentation (15 minutes), or as a poster.
For long and short presentations, 8 pages will be assigned in the published
proceedings. A poster presentation will be assigned 4 pages. Papers
exceeding the page limit will be charged 50 Euro per page in excess. If the
paper is accepted, at least one of the authors must pre-register and pay the
conference fee before the deadline for submitting the camera-ready paper.
Otherwise the paper will not be published in the proceedings.
Check List:
Prospective authors should check that the following information are included
while submitting the paper(s) for refereeing purpose.
() The paper and its title page should not contain the name(s) of the author(s),
or their affiliation
() The first page of the paper should the following information
* Title of the paper
* Track Area
* Conference topic area (write the most appropriate topic area)
* Up to six keywords
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Steering Committee:
Chairman: Lech Józwiak, Eindhoven Univ. of Technology (NL)
Krzysztof Kuchcinski, Lund U. (SE)
Antonio Nunez, U. Las Palmas (ES)
Program Chair: Venki Muthukumar, UNLV, USA
Deputy Program Chair: H. Kubatova, Cz. TU. in Prague, (CZ)
Organizing General Chair: Prof. Ivica Crnkovic, U. Mälardalen (SE)
Organizing Local Chair: Dr. Zoran Kalafatic, U. of Zagreb, Croatia
Program Committee:
Visit http://www.dsdcong.org/ for a complete list of Program Committee Members.
Contact Information:
Program Chair: Dr Venki Muthukumar
Department of Electrical and Computer Engineering
University of Nevada Las Vegas
4505 Maryland Parkway, Box 4026
Las Vegas, NV 89154-4026, USA
Phone: +1 702 895 3566
Fax: +1 702 895 4075
email: venki@dsdconf.org
DSD’06 web page: http://www.dsdconf.org/
Euromicro web page: http://www.euromicro.org/
DSD web page: http://www2.ele.tue.nl/dsd/

Symposium on Architectures for Networking and Communications Systems

TIPPINST – The ANCS has found a new home page and now contains information on the upcoming programme of events. The conference will take place in Princeton University from Oct 26 – 28th 2005. This conference has evolved from the HPCA Network Processor Conferences
The following is taken from their web site
http://www.cesr.ncsu.edu/ancs/home.html
NCS is new research conference that focuses on the design of the hardware and software components used to create modern communication networks. The combination of increasing network line speeds and expanding functional requirements pose continuing and growing challenges for system designers. New technology elements, including network processors, content addressable memories, configurable logic and special-purpose components offer new opportunities for meeting these challenges, but also raise a variety of new issues. ANCS focuses on architectures for networking and communication in the broad sense, including novel architectures, architectural support for advanced communication, algorithms and protocols for advanced architectures, software and applications for next-generation networking architectures, and methodology and benchmarking for evaluating advanced communication architectures.

Call for Papers ISSC 2005 Sep 1 – 2 Dublin City University

TIPPINST – I just received notification on Friday that the ISSC conference is going ahead this year. The deadlines are extemely tight as papers have to be submitted by July 12th !
This year’s Irish Signals and Systems Conference will be held in Dublin City University on the 1st and 2nd of September. Authors are invited to submit conference papers describing original research in the areas of signals and systems.
Topics of interest include, but are not limited to:
Signal Processing Statistical
Signal and Array Processing
Multimodal Signal Processing
I.C.s for Signal Processing and Control
Speech and Audio Processing
Control Systems Theory and Applications
Communication Systems and Networks
Linear and Non-linear Circuit Theory
Computer Vision and Pattern Recognition
Mathematical System Theory
ISSC 2005