Archive for Simulation and Design

Demystifying Genetic Algorithms Paper – An Educational Genetic Algorithms Learning Tool

I came across this paper while researching Genetic Algorithms. Liao et al have done an excellent job of demystifying GA’s and how they work. Having dipped into a few books on GA’s I would recommend this paper as a starting point.
An Educational Genetic Algorithms Learning

Network Processor – Call for Papers – HPCA-12

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.
Topics of interest include, but are not limited to: ·
Processor architectures ·
Cache and memory systems ·
Parallel computer architectures ·
Impact of technology on architecture ·
Power-efficient architectures and techniques ·
High-availability architectures ·
High-performance I/O systems ·
Embedded and reconfigurable architectures ·
Interconnect and network interface architectures ·
Network processor architectures ·
Innovative hardware/software trade-offs ·
Impact of compilers on architecture ·
Performance evaluation of real machines
Authors should submit an abstract before Monday, July 11, 2005, 9pm PST. They should submit the full version of the paper before Monday, July 18, 2005, 9pm PST. No extensions will be granted. The full version should be a PDF file that does not exceed 6,000 words according to the instructions in
Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Papers should be submitted for blind review. Please indicate whether the paper is a student paper for best student paper nominations.Papers will be evaluated based on their novelty, fundamental insights, and potential for long-term contribution.
New-idea papers are encouraged.
Submission issues should be directed to the program chair at Workshop and tutorial submissions should be directed to the workshop and tutorial chair.
Important dates·
Abstract submission deadline :
July 11, 2005, 9pm PST (firm deadline) ·
Paper submission deadline:
July 18, 2005, 9pm PST (firm deadline) ·
Workshop and tutorial proposals due:
August 12, 2005 ·
Author notification: October 7, 2005
Sponsored by the IEEE Computer Society TC on Computer Architecture

Adding instructions to the Simplscalar decode tree.

The simplscalar decode tree for instructions can be at first quiet daunting.
Tracing the decode pattern is a pen and paper exercise.
e.g the range of instructions that start with 0x06 are defined as
DEFLINK(MEMREGPOST_LINK, 0x06, “memregpost_link”, 20, 0x0f)
This means shift the inst that start with 0x06 e.g 0x06000000 and examine bits 20 – 23
After the connect code we have an entry for 0x00 this means that if bits 20 -23 are 00 this will match and generate an opcode for this instruction
e.g 0x06000000
#define STR_R_IMPL \
etc etc
The challenge facing anyone is to add extra opcodes that are meaningful.
If one examines the 0x06 range of opcodes it is evident that instructions such as
0x06000100, 0x06000200 are unused.
So how do we use them in Simplescalar?
Well what we need to do is modify arm.def to examine bits 8 – 11 first, if these bits are 0 then they are the original instructions defined under memregpost. If not they are our new instructions.
A statement such as the one below takes care of examining bits 8 -11 of an inst that starts with 0x06
DEFLINK(MEMREGPOST_LINK, 0x06, “memregpost_link”, 8, 0x0f)
We now need to ensure that 0x06 instructions whose bits are 0 from pos 8 to 11 are directed to a different part of the decode tree. The deflink code below will be executed if the bits are 0 and will examine bits 20 – 23 of the 0x06 inst in the connect section.
In the example below inst 0x06000000 will be associated with a deflink to a new tree where the isnt str%c will be associated with 0x06000000. While inst 0x06000100 will be associated with the inst demo because bits 8 to 11 equate to 1
DEFLINK(MEMREGPOSTNEW_LINK, 0x00, “memregpostnew_link”, 20, 0x0f)
#define demo_IMPL \
DEFINST(demo, 0x01,
“demo%c”, “%d,%n,%m”,
#define STR_R_IMPL \
“str%c”, “%d,[%n],-%m!”,
We also need to to add these new opcodes to your gas see for more details on how to hack GAS.

Hacking Simplescalar – Adding Instructions

I’ve been very busy for the past few weeks working on Simplescalar. As a result this site has suffered.
My bookmarks for Simplescalar have now grown into some essential how-to and readmes for the adding instructions to simplescalar.
The first place to look for help on this is the simplescalar website as they have a readme on the machine.def file format.
The information is very detailed but adding the instruction part was slightly confusing. I came across some other sites however that provided more info.
Simplescalar Archives – I would like to thank Guri Sohi at the University of Wisconsin-Madison for restoring the email archives.
YongKhui Han’s page – describes how modify the compiler and simplescalar to recognise new instructions
Laura Pozzi a a PostDoc researcher in the LAP, Processor Architecture Laboratory, at EPFL, Lausanne describes how to add a new resource to simplescalar
Inline assembly is sometimes necessary with simplescalar the GCC inline assembly how to is a useful resource.

SimpleScalar – An Open Source Simulator for Academics

I am currently experimenting with SimpleScalar which I why I have been updating my site for the past few days.
SimpleScalar can emulate the Alpha, PISA, ARM, and x86 instruction sets. The tool set includes a machine definition infrastructure that permits most architectural details to be separated from simulator implementations. All of the simulators distributed with the current release of SimpleScalar can run programs from any of the above listed instruction sets. Complex instruction set emulation (e.g., x86) can be implemented with or without microcode, making the SimpleScalar tools particularly useful for modeling CISC instruction sets.
SimpleScalar was created by Todd Austin. Development began while he was a Ph.D. student at the University of Wisconsin in Madison. Early versions of the tool set included contributions by Doug Burger and Guri Sohi. Today, SimpleScalar is developed and supported by SimpleScalar LLC.
According to Bill Yuricks website on Computer Architecture web sites
“in 2000 more than one third of all papers published in top computer architecture conferences used the SimpleScalar tools to evaluate their designs”
It was this comment that prompted me to have a look at the tool.
SimpleScalar LLC distribute their software under an open source model, trusting that the users will license the software that they use. The software is free for academic and research use.
The tool set is distributed with all source code, making it possible for users extend SimpleScalar, and to adapt existing models to their own ideas.
SimpleScalar Tool Set

Spim – An Open Source RISC Simulator

As part of my phd research I require an open source RISC simulator. The candidate that seems to fit that profile is Spim.
Spim implements almost the entire MIPS32 assembler-extended instruction set. (It omits some complex floating point comparisons and rounding modes and details of the memory system page tables.) The MIPS architecture has several variants that differ in various ways (in particular, the MIPS64), which means that spim will not run programs compiled for all MIPS-based processors.
It was developed by James Larus, formerly: Professor, Computer Sciences Department, University of Wisconsin-Madison,currently: Senior Researcher at Microsoft Research.
Spim has the option to be cycle accurate and is available for Windows and Linux platforms.
If anyone is aware of any other RISC cycle accurate simulators, please email lnoonan_blog at

ACM – Concurrent Hardware-Software Design Methods Call for Papers

ACM transaction on embedded computing have a call for papers on the following.
SoC design complexity threatens continuation of current design schemes. In fact, designing SoC requires concurrent design of complex embedded software and a sophisticated hardware platform that may include several heterogeneous CPU subsystems. The lack of early coordination between different teams belonging to different cultures causes delay and cost overheads that are no more acceptable for the design of embedded systems. Programming models have been used to coordinate software and hardware communities for the design of classic computers. A programming model provides an abstraction of HW-SW interfaces and allows concurrent design of complex systems made of sophisticated software and hardware platforms. Examples include API at different abstraction levels, RTOS libraries, drivers, typically summarized as hardware dependent software. This abstraction smoothes the design flow and eases interaction between different teams belonging to different cultures, hardware, software and system architecture. This special issue addresses the application of this concept to SoC with emphasis on practical issues.
Submission date is Feb 15 2005
More details can be found here

Papers on real time and embedded Linux has published proceedings from the Sixth Real-Time Linux Workshop held in Asia, at the Nanyang Technological University in Singapore.
The papers span a broad range of topics ranging from fundamental real-time technologies, to applications, to hardware, to tools. As usual, the conference was organized by the Real-Time Linux Foundation.
25 papers on real-time and embedded Linux

Debian Linux cross compile tool reports on an open source project that could be of benefit for my PhD research.
Scratchboxis an open source project to simplify cross-platform software compilation. They have recently made several advances that may interest embedded device developers. The project is helping Debian ARM strive for parity with Debian x86 by enabling package maintainers to build native ARM applications on fast x86 PCs, without modifying package build scripts
Cross-compile tool helps Debian ARM Linux catch up with x86

Cafe et croissant

I am now in sunny Renne attending the 30th Euromicro and DSD Symposium at IFSIC Campus universitaire de Beaulieu. I can confirm that the croissants taste better in France than they do in Ireland.
With speakers from as far flung places as Australia, Ukraine, USA it should make for a rewarding experience.