Simulation and Design: July 2004 Archives

SANTA CLARA, Calif. July 7, 2004 - Tensilica, Inc. announced that it has achieved a major design automation breakthrough the automated design of optimized configurable processors from standard C code using the company's new XPRES (Xtensa PRocessor Extension Synthesis) Compiler.

This tool enables the rapid development of optimized system-on-chip (SOC) devices without requiring designers to hand code their hardware using design languages like VHDL and Verilog.

Instead, designers input the original algorithm that they're trying to optimize, written in standard ANSI C/C , and the XPRES Compiler, coupled with Tensilica's automated processor generation technology, automatically generate an RTL (register transfer level) hardware description and associated software tool chain. In less than an hour, the resulting hardware block is delivered in the form of a pre-verified Xtensa LX processor core.

Additionally, the generated RTL fully rivals the performance and efficiency of hand-coded RTL blocks with many concurrent operations, efficient data types, and optimized multiple wide deep pipe

XPRES Compiler Automates Processor and RTL Design from Standard C Code

I am currently attending ISSC 2004 where I was presenting some research in the area of system design.

Again the main attraction for me this year is the chance to discuss concepts with my peers across a variety of colleges.

The two most common question I encountered today regarding my work of modelling the IXP1200 using OO techniques, where.

1. Why do you want to create a s/w model of a silicon design?

2. What is UML ?

I found that my sequence diagrams and class diagrams really brought home the idea of why OO techniques are so powerful.

The questions I recieved certainly helped to focus my thoughts as to what should be done next.

Queens University should be congratulated for the excellent conference that they are hosting.